This invention relates to a semiconductor device and, more particularly, to a structure of a bipolar transistor and a process of fabrication thereof.
A bipolar transistor is an important circuit component of a semiconductor integrated circuit device used for a communication network in the giga-hertz band. The switching speed of the bipolar transistor is mainly dominated by the thickness of the base region where the carrier passes through. The thinner the base region is, the faster the switching action is. The resistance of the emitter, base and collector regions and the parasitic capacitances coupled to the emitter/base and collector regions affect the switching speed of the bipolar transistor. These factors strongly relate to the miniaturization and the accuracy of patterning technologies used in the fabrication process of the bipolar transistor. However, a self-aligning technology between the emitter region and the base contact region makes the improvement in switching speed free from the accuracy of patterning technologies. The self-aligning technology is disclosed by Tak H. Ning et al. in xe2x80x9cSelf-Aligned Bipolar Transistors for High-Performance and Low-Power Delay VLSIxe2x80x9d, IEEE Transactions on Electron Devicesxe2x80x9d, vol. ED-28, No. 9, September 1981, pages 1010 to 1013.
FIGS. 1A to 1G illustrate a typical example of the process of fabricating the self-aligned bipolar transistor of the n-p-n type. The prior art process starts with preparation of a p-type silicon substrate 1. A photo-resist ion-implantation mask (not shown) is prepared on the major surface of the p-type silicon substrate 1 by using lithographic techniques, and an area is uncovered with the photo-resist ion-implantation mask. Arsenic is ion implanted into the area, and the photo-resist ion-implantation mask is stripped off. The ion-implanted arsenic is activated in nitrogen ambience at 1000 degrees to 1200 degrees centigrade for 2 to 4 hours, and forms a heavily doped n-type buried layer 1b. 
A photo-resist ion-implantation mask (not shown) is patterned on major surface of the p-type silicon layer 1a by using the lithographic techniques, and another area around the heavily doped n-type buried region 1b is uncovered with the photo-resist ion-implantation mask. Boron is ion implanted into the exposed area, and the photo-resist ion-implantation mask is stripped off. The ion-implanted boron is activated in a the nitrogen atmosphere at 900 degrees to 1100 degrees centigrade for 30 minutes to an hour, and forms a heavily doped p-type buried region 1c as shown in FIG. 1A. The heavily doped p-type buried region 1c electrically isolates the self-aligned bipolar transistor from another circuit component.
N-type silicon is epitaxially grown to 2 microns thick on the major surface of the p-type silicon substrate 1a, and the p-type silicon substrate 1a is overlain by an n-type epitaxial silicon layer 2a. A p-type channel stopper region 2b is formed in the n-type epitaxial silicon layer 2a, and is merged with the heavily doped p-type buried layer 1c as shown in FIG. 1B.
A thick field oxide layer 3 is selectively grown to 600 nanometers thick by using LOCOS (local oxidation of silicon) technology. The growth of the thick field oxide layer 3 is carried out at 1000 degrees centigrade, and consumes long time. While the heat is growing the thick field oxide layer 3, the boron and the arsenic are diffused from the heavily-doped p-type buried layer/p-type channel stopper region 1c/2b and the heavily doped n-type buried layer 1b, respectively, and the n-type buried layer 1b expands as shown in FIG. 1C. As a result, the expansion of the n-type buried layer 1b decreases the thickness of the n-type epitaxial layer 2a inside of the thick field oxide layer 3.
Subsequently, phosphorous is thermally diffused into a narrow area of the n-type epitaxial layer 2a, and reaches the heavily doped n-type buried layer 1b. The phosphorous forms an n-type collector contact region 4a merged into the heavily doped n-type buried layer 1b. 
Silicon oxide is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and forms a silicon oxide layer. A photo-resist etching mask is patterned on the silicon oxide layer through the lithography, and the silicon oxide layer is selectively etched away. The silicon oxide layer is patterned into a silicon oxide mask 5a. The n-type collector contact region 4a is covered with the silicon oxide mask 5a; however, the n-type epitaxial silicon layer 2a is exposed to an opening of the silicon oxide mask 5a as shown in FIG. 1D.
Subsequently, polysilicon is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and p-type dopant impurity is introduced into the polysilicon layer. In this instance, boron is introduced into the polysilicon through an in-situ doping technique, or boron is ion implanted into the amorphous silicon layer. The boron-doped polysilicon layer is used for a base electrode as described hereinlater.
In order to isolate the base electrode from an emitter electrode, silicon nitride is deposited over the boron-doped polysilicon layer, and the boron-doped polysilicon layer is overlain by a silicon nitride layer. A photo-resist etching mask (not shown) is patterned on the silicon nitride layer, and the silicon nitride layer and the boron-doped polysilicon layer are selectively etched away so as to form a base electrode 4b covered with an inter-level insulating layer 5b as shown in FIG. 1E.
A photo-resist etching mask (not shown) is patterned on the inter-level insulating layer 5b, and has an opening over a central area of the n-type epitaxial silicon layer 2a. Using the photo-resist etching mask, the inter-level insulating layer 5b and the base electrode 4b are selectively etched away so as to form an opening 5c over the central area of the n-type epitaxial layer 2a. 
The resultant semiconductor structure is treated with heat, and the boron is diffused from the base electrode 4b into the central area of the n-type epitaxial layer 2a. The boron forms a graft base region 4c beneath the base electrode 4b. Boron or boron difluoride (BF2) is ion implanted into the central area of the n-type epitaxial silicon layer 2a, and forms an intrinsic base region 4d as shown in FIG. 1F.
Silicon oxide is deposited over the entire surface of the resultant semiconductor structure, and forms a silicon oxide layer topographically extending over the resultant semiconductor structure. The silicon oxide layer is anisotropically etched away without a photo-resist etching mask, and side wall spacers 5d/5e are left on the inner and outer side surfaces of the base electrode 4b. The side wall spacer 5d on the inner side surface covers a peripheral area of the intrinsic base region 4d, and a central area of the intrinsic base region 4d is still exposed.
Heavily arsenic-doped polysilicon is grown on the entire surface of the resultant semiconductor structure, and a heavily arsenic-doped polysilicon layer is held in contact with the central area of the intrinsic base region 4d. A photo-resist etching mask (not shown) is patterned on the heavily arsenic-doped polysilicon layer, and the heavily arsenic-doped polysilicon layer is patterned into an emitter electrode 4e. 
The arsenic is thermally diffused from the emitter electrode 4e into the central area of the intrinsic base region 4d by using a lamp annealing, and forms an emitter region 4f. 
Finally, a collector contact hole is formed in the silicon oxide layer 5a, and a collector electrode 4g is held in contact with the corrector contact region 4a through the collector contact hole as shown in FIG. 1G.
Thus, the side wall spacer 5d causes the emitter region 4f to be exactly nested into the intrinsic base region 4c, and the emitter region 4f never enters into the graft base region 4c. However, the n-type epitaxial silicon layer 2a is too thick to improve the switching speed. In detail, it is important to reduce the collector resistance for a high speed switching action, and the reduction of the collector resistance is achieved by a thin n-type epitaxial layer 2a. However, if the n-type epitaxial layer 2a is thin, the n-type dopant impurity is diffused from the heavily doped n-type buried layer 1b into the thin epitaxial layer 2a during the heat treatment for the thick field oxide layer 3, and increases the dopant concentration of the n-type epitaxial layer 2a. A lightly doped n-type region called a xe2x80x9cflat zonexe2x80x9d is necessary for the collector region, and the n-type dopant impurity diffused from the heavily doped n-type buried layer 1b damages the flat zone. This results in deterioration of the bipolar transistor. Thus, the diffusion from the heavily doped n-type buried layer 1b does not allow the manufacturer to make the n-type epitaxial layer 2a thin, and the thick n-type epitaxial layer 2a sets a limit on the switching speed of the prior art bipolar transistor.
A problem of the prior art process is the lithographic step is repeated twice for the heavily doped n-type buried layer 1b and the heavily doped p-type buried layer 1c. The prior art process is complex, and increases the production cost of the prior art bipolar transistor.
It is therefore an important object of the present invention to provide a bipolar transistor which is improved in switching speed.
It is also an important object of the present invention to provide a simple process of fabricating the bipolar transistor.
To accomplish the object, the present invention proposes to grow a lightly doped epitaxial silicon layer in a recess formed after a growth of a field oxide layer.
In accordance with one aspect of the present invention, there is provided a bipolar transistor fabricated on a silicon substrate of a first conductivity type, comprising: a heavily doped impurity region formed in a surface portion of the silicon substrate and having a second conductivity type opposite to the first conductivity type, a recess being formed in a surface portion of the heavily doped impurity region; a lightly doped epitaxial silicon layer of the second conductivity type filling the recess and having a flat zone substantially constant in dopant concentration below a first surface portion thereof; a base region of the first conductivity type formed in the first surface portion of the lightly doped epitaxial silicon layer; a heavily doped collector contact region of the second conductivity type formed in a second surface portion of the lightly doped epitaxial silicon layer contiguous to the flat zone; and an emitter region of the second conductivity type formed in a surface portion of the base region.
In accordance with one preferred embodiment of the above described bipolar transistor, the surface portion of the silicon substrate is formed by a (100) crystal plane or a crystal plane equivalent to a (100) crystal plane, and the heavily doped impurity region has a first surface defining a bottom of the recess and formed by a (100) crystal plane or a crystal plane equivalent to a (100) crystal plane. In another embodiment, the heavily doped impurity region further has a second surface defining a side of the recess and formed by a (111) crystal plane, a (110) crystal plane or a crystal plane equivalent to a (111) crystal plane or a (110) crystal plane.
In accordance with another aspect of the present invention, there is provided a process of fabricating a bipolar transistor, comprising the steps of: a) preparing a silicon substrate of a first conductivity type; b) introducing a first dopant impurity into a surface portion of the silicon substrate so as to form a heavily doped impurity region of a second conductivity type opposite to the first conductivity type; c) thermally growing a field insulating layer occupying at least an outer peripheral area of the heavily doped impurity region; d) selectively removing a central portion of the heavily doped impurity region for forming a recess therein; e) epitaxially growing a single crystal silicon in the recess so as to form a lightly doped epitaxial silicon layer of the second conductivity type; and f) forming a base region in a surface portion of the lightly doped epitaxial silicon layer and an emitter region in a surface portion of the base region.